1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically to a structure for reading data of a non-volatile memory cell.
2. Description of the Background Art
A conventional non-volatile semiconductor memory device basically reads data using a differential amplifier.
The structure of a sense amplifier for reading data in the conventional non-volatile semiconductor memory device will be described with reference to FIG. 12. A memory cell from which data is read is referred to as an array cell 6a, and a reference cell used for detecting data of array cell 6a is referred to as a reference cell 6b. 
Array cell 6a is connected to a current detecting portion 3a through Y gates (NMOS transistors) 4a and 5a, and reference cell 6b is connected to current detecting portion 3a through Y gates (NMOS transistors) 4b and 5b. 
Current detecting portion 3a, Y gates 4a, 5a and array cell 6a are collectively shown as a pre-sense amplifier portion 1a. Current detecting portion 3b, Y gates 4b, 5b and reference cell 6b are collectively shown as a pre-sense amplifier portion 1b. 
Current detecting portion 3a includes PMOS transistors P1 and P2 as well as NMOS transistors N1 and N2. Transistors P2 and N2 are connected in series between a power supply node receiving a power supply voltage Vcc and a node GND receiving a ground voltage. Transistor P2 has its gate receiving an enable signal E controlling activation/inactivation, whereas transistor N2 has its gate connected to a node Z1.
Transistors P1 and N2 are connected in series between the power supply node and node Z1, and transistor N1 has its gate connected to a connection node of transistors P2 and N2.
When a word line VWL for driving the gate of array cell 6a is activated and Y gates 4a, 5a are turned on, the drain of array cell 6a is connected to current detecting portion 3a (selection of array cell 6a).
Current detecting portion 3b includes PMOS transistors P3 and P4 as well as NMOS transistors N3 and N4. Transistors P4 and N4 are connected in series between the power supply node receiving the power supply voltage and node GND. Transistor P4 has its gate receiving enable signal E, and transistor N4 has its gate connected to a node Z3.
Transistors P3 and N3 are connected in series between the power supply node and node Z3, and transistor N3 has its gate connected to the connection node of transistors P4 and N4.
When word line VWL for driving the gate of reference cell 6b is activated and Y gates 4b, 5b are turned on, the drain of reference cell 6b is connected to current detecting portion 3b. 
It is noted that although the Y gates are shown as two stages of NMOS transistors, the number of stages or elements are not limited to this.
The current of array cell 6a detected by current detecting portion 3a is transferred to an NMOS diode N5 through a PMOS transistor P5 connected to form a current mirror 7a with transistor P1. A signal received by the gates of transistors P1 and P5 and a node connected to the gates are collectively indicated as Z2. A reference character Icell represents the detected current flowing through transistor P5.
The current of reference cell 6b detected by current detecting portion 3b is transferred to an NMOS diode N6 through a PMOS transistor P6 connected to form a current mirror 7b with transistor P3. A signal received by the gates of transistors P3 and P6 and a node connected to the gates are collectively indicated as Z4. Reference character Iref represents the detected current flowing through transistor P6.
Transistors P5 and P6 are respectively connected to NMOS diodes N5 and N6 at a first input node A and a second node B of a differential amplifier 2.
Current Icell is converted to a voltage Vcell0 by NMOS diode N5 which is a current voltage converting element. Current Iref is converted to voltage Vref0 by NMOS diode N6 which is also a current voltage converting element.
It is noted that, with regard to a circuit from the current detecting portion to the current voltage converting portion, similar elements are used for both of an array cell and a reference cell.
Differential amplifier 2 includes PMOS transistors P11, P12, P13 and NMOS transistors N11, N12, N13. Transistors P11 and N11 are connected in series between the power supply node and a node Z5, and transistor N11 has its gate connected to a node A. Transistors P12 and N12 are connected in series between the power supply node and node Z5, and transistor N12 has its gate connected to node B.
Transistor N13 is connected between node Z5 and node GND, and has its gate receiving a control signal IREF. Transistor P13 is connected between a connection node of transistors P11, N11 and a connection node of transistors P12, N12, and has its gate receiving a control signal IREF2.
Differential amplifier 2 detects a small voltage difference between nodes A and B (a difference between voltage Vcell0 and voltage Vref0), and outputs the detection result from a connection node OUT of transistors P12 and N12. An output circuit (not shown) converts the output from differential amplifier 2 to a signal at a logic level for output.
In a conventional sense amplifier circuit, a diode is used for the voltage converting portion in order to ultimately convert the detected current to a voltage. Hence, the voltage difference between the array cell and reference cell is not so large. Thus, differential amplifier 2 is used to detect the difference of the small voltage.
However, if a multi-level cell is used which allows a plurality of pieces of information to be stored in a single memory cell depending on a situation of a threshold value, a value of current to be detected would be even smaller. Thus, the conventional sense amplifier circuit cannot properly detect a voltage difference.
By contrast, a gain may be obtained with differential amplifiers connected in two stages to provide enhanced detection sensitivity. However, with the greater number of differential amplifiers, a delay time would be longer because of operations of the differential amplifiers in two stages. As a result, a greater amount of current would be consumed by a larger circuit.
An object of the present invention is to provide a semiconductor memory device capable of precisely reading data with a simple circuit structure.
A non-volatile semiconductor memory device according to one aspect of the present invention includes: a non-volatile memory cell; a reference cell determining stored data of the memory cell; a differential amplifier detecting a difference between voltages at first and second input nodes; a first current voltage converting element connected to the first input node for converting a first read current from the memory cell to a voltage; a second current voltage converting element connected to the second input node for converting a second read current from the reference cell to a voltage; and a gain adjusting circuit adjusting a detection sensitivity of a differential amplifier by adjusting values of the first and second read currents.
Preferably, the first and second current voltage converting elements respectively include diode elements, and the gain adjusting circuit includes a constant current circuit for supplying offset currents to the first and second input nodes.
In particular, the constant current circuit includes a first constant current circuit connected to the first input node, and a second constant current circuit connected to the second input node. The first and second constant current circuits supply substantially the same current.
Preferably, the gain adjusting circuit includes: a drive circuit generating a current with a value lower than that of the second read current based on the second read current for converting the generated current to a voltage; a first element connected to the first input node for supplying a first offset current based on the voltage obtained from the drive circuit; and a second element connected to the second input node for supplying a second offset current based on the voltage obtained from the drive circuit. The first and second offset currents have substantially the same value.
Preferably, the gain adjusting circuit includes: a drive circuit generating a current with a value lower than that of the second read current based on the second read current for converting the generated current to a voltage; a first element connected to the first input node for supplying a current with a value lower than that of the second read current to the second current voltage converting element; and a second element connected to the second input node for supplying an offset current based on the voltage obtained from the drive circuit.
Preferably, the first and second current voltage converting elements include resistive elements, and the gain adjusting circuit includes a constant current circuit supplying offset currents to the first and second input nodes.
A non-volatile semiconductor memory device according to another aspect of the present invention includes: a non-volatile memory cell capable of operating in n storage states (n is an integer of at least 3); k (k is an integer of at least 2) reference cells for determining the n storage states; k first current voltage converting elements each converting a first read current of the memory cell to a voltage; k second current voltage converting elements converting k second read currents from the k reference cells to voltages; k differential amplifiers detecting differences between an output from the first current voltage converting element and respective outputs from the k second current voltage converting elements; and a gain adjusting circuit adjusting detection sensitivities of k differential amplifiers by adjusting the values of the k second read currents and the first read current.
Preferably, each of the first current voltage converting element and the k second current voltage converting elements includes a diode element, and the gain adjusting circuit includes a constant current circuit for reducing an input current to the first current voltage converting element and at least one of k second current voltage converting element.
Preferably, the gain adjusting circuit includes a constant current circuit changing the input current to each of the first current voltage converting element and k second current voltage converting elements according to the detection sensitivities of the k differential amplifiers. The constant current circuit causes the input current to respective k second current voltage converting elements to have substantially the same value.
Preferably, the constant current circuit includes a circuit for generating (kxe2x88x92j) offset currents using j (j is an integer of at least 1 and at most (kxe2x88x921))of the k second read currents, and reduces input current to (kxe2x88x92j) second current voltage converting elements by (kxe2x88x92j) offset currents.
Preferably, the first current voltage converting element and k second current voltage converting elements respectively include resistive elements, and the gain adjusting circuit includes a constant current circuit for reducing input currents to the first current voltage converting element and at least one of k second current voltage converting elements.
As described above, according to the non-volatile semiconductor memory device of the present invention, a detection sensitivity is enhanced.
According to the non-volatile semiconductor memory device of the present invention, the detection sensitivity can be enhanced without increasing the size of the circuit structure.
According to the non-volatile semiconductor memory device of the present invention, a detection sensitivity can be enhanced without decreasing the operation speed.
According to the non-volatile semiconductor memory device of the present invention, a detection sensitivity can be enhanced without increasing power consumption.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.